The present invention is related to configurable interconnection networks in integrated circuits and, in particular, to the FPGA (Field Programmable Gate Array) cores which are embedded in integrated circuits. The FPGA core can provide configurable interconnections between functional circuit blocks, particularly a computing element such as processor core, or itself provide a configurable functional circuit block, in the integrated circuit.
An FPGA is an integrated circuit with logic cells and an interconnection network between the logic cells which are both configurable so that the function of the FPGA is adapted to a user's application. The user programs the integrated circuit for his or her application and hence the term, “field programmable.” For FPGAs based on SRAM (Static Random Access Memory) cells to hold the configuration bits, the configuration of the FPGA can be changed by the user for multiple applications of the electronic system. For configurable cores based on single-mask customization, the FPGA can only be configured once by the user.
With shrinking geometries in semiconductor technology, FPGAs are beginning to be embedded with functional circuit blocks in ASICs (Application Specific Integrated Circuits). Such blocks may include a processor, memory, and peripheral elements in a so-called System-on-a-Chip (SOC), or even multi-processor elements of a parallel computing integrated circuit, for example. The main configurable portion of the FPGA, termed an FPGA core, is embedded in the ASIC to configurably interconnect the various functional circuit blocks of the ASIC or to form another functional circuit block of the integrated circuit. This block is programmable by the user (or the manufacturer of the ASIC) to make the integrated circuit flexible in its application.
Heretofore, FPGA cores have been embedded into an ASIC with conventional, i.e., “hard-wired,” interconnects wiring to other functional circuit blocks according to the particular design of the ASIC. Given the flexible nature of an ASIC with one or more FPGA cores, it is possible that the application of the ASIC may change. The FPGA cores may be reprogrammed but the wiring remains, interfering partially or completely with the ASIC's adaptability to the new application.
The present invention is directed toward this problem and offers an effective way of adding even more flexibility to embedded FPGA cores.